There has been conventionally proposed an example of a D/A conveter which effects the D/A conversion of a product of a plurality of digital input signals, e.g. as shown in FIG. 1. Referring to FIG. 1, reference numeral 1 designates an input terminal to which a digital signal is supplied and this input terminal 1 has n terminals 1.sub.0, 1.sub.1, 1.sub.2, . . . , 1.sub.n corresponding to the number of bits of a digital signal to be inputted thereto The digital signal having n bits is parallelly inputted such that the most significant bit (MSB) thereof is supplied to the terminal 1.sub.0, the bit next to the MSB to the terminal 1.sub.1, respective bits are supplied sequentially to the respective terminals in the same manner, and finally the least significant bit (LSB) thereof is supplied to the terminal 1.sub.n.
The n-bit digital signals simultaneously inputted to the terminals 1.sub.0 -1.sub.n are supplied to a data register 2 through input terminal groups 3 and 4 in predetermined conditions. To be specific, the input terminal groups 3 and 4 respectively have m and (m-n-1) input terminals 3.sub.0 -3.sub.m and 4.sub.0 -4.sub.m. The terminal 1.sub.0 is connected only to the terminal 3.sub.0, and the terminal 1.sub.n only to the terminal 4.sub.m. Further, the terminal 1.sub.1 is connected to input terminals 3.sub.1 and 4.sub.0, the terminal 1.sub.2 to terminals 3.sub.1 and 4.sub.1, and in the same manner, respective terminals of the input terminal group 1 are connected to respective input terminals of the input terminal groups 3 and 4.
Therefore, the input terminal 3.sub.0 the data register 2 is supplied with the most significant bit of the input digital signal, the input terminal 3.sub.1 bit next to the most significant bit of the same input digital signal, and in the same manner as above, the respective input terminals 3.sub.2, 3.sub.3, . . . , 3.sub.m are supplied with the respective bits of the digital input signal. Further, the input terminal 4.sub.0 of the data register 2 is supplied with the second most significant bit of the input digital signal, the input terminal 4.sub.1 with the third significant bit of the same, and in the same manner, respective input terminals 4.sub.2, 4.sub.3, . . . , 4.sub.m are sequentially supplied with the respective bits of the digital input signal. At the last, the input terminal 4m is supplied with the least significant bit of the input digital signal supplied to the terminal 1m.
The data register 2 switches the digital signals inputted to the input terminal groups 3 and 4 and delivers the same to an output terminal group 5 which has m output terminals 5.sub.0, 5.sub.1, . . . , 5.sub.m. The digital signal outputted to the output terminal group 5, i.e. the signal inputted to the input terminal group 3 or that inputted to the input terminal group 4, is selected by a change-over control signal supplied from a control circuit 7 to the data register 2 through its control terminal 6.
Therefore, delivered to the output terminal group 5 is, in response to the switching operation by the data register 2, either the digital signal from the input terminal group 3, that is, the digital signal comprising from the most significant bit to the second least significant bit or the digital signal from the input terminal group 4, that is, the digital signal comprising from the second most significant bit to the least significant bit.
The manner which of the digital signals supplied to the input terminal groups 3 and 4 is delivered to the output terminal 5 of the data register 2 by switching the same is based upon the result of a determination made as to whether or not the information area of the inputted digital signal exceeds a predetermined information area. Information indicative of the information area of the inputted digital signal can be obtained on the basis of a predetermined number of digits of bit information including the MSB of the inputted digital signal.
The above-mentioned determination operation is effected by the control circuit 7. This control circuit 7 determines whether or not the information area of the inputted digital signal exceeds the predetermined information area on the basis of the predetermined number of digits of bit information including the most significant bit of the inputted digital signal and generates an information area signal (a change-over control signal) according to the determination result.
The signal generated by the control circuit 7 is supplied to the control terminal 6 of the data register 2 and a control terminal 9 of another data register 8, as will be later described. The data registers 2 and 8 carry out the changing operation in response to the information area state in the digital input signals. To be specific, if the digital input signal occupies an information area which is more than one half of the full scale, the data register 2 delivers the digital signal in the input terminal group 3 to the output terminal group 5. On the other hand, if the digital input signal is the signal of the information area less than one half of the full scale, the data register 2 delivers the digital signal in the input terminal group 4 to the output terminal group 5.
The output from the data register 2 is supplied to a latch circuit 10 and this latch circuit 10 latches the digital signal from the data register 2 and supplies the same to a D/A converter 12 at the time a latch signal is applied thereto from a terminal 11.
The D/A converter 12 is a multiplication type one which is provided with an external reference input terminal 13. To this input terminal 13 is supplied an external reference signal generated from another D/A converter 14.
The data register 8 has two input terminal groups 15 and 16 such that two digital signals, generated from a fixed data generating circuit 17, respectively indicative of different data are suppied thereto. To an output terminal group 18 of the data register 8, there is delivered in response to the change-over operation effected by the data register 8, the digital signal indicative of one data from the fixed data generating circuit 17, or the digital signal indicative of the other data from the fixed data generating circuit 17.
The digital signal outputted from the data register 8 is latched by a latch circuit 19 and then supplied to the D/A converter 14 as an input signal, at the time the latch signal is supplied from the terminal 11 to the latch circuit. The D/A converter 14 converts the inputted digital signal into an analog signal and supplies the converted analog signal to the input terminal 13 of the D/A converter 12 as an external reference input signal (external reference voltage).
When the digital signal inputted to the input terminal 1 is the signal of an information area larger than one half of the full scale and the data register 2 delivers the digital signal in the input terminal group 3 to the output terminal group 5, the data register 8 outputs, to the output terminal group 18, the digital signal indicative of the one data supplied from the fixed data generating circuit 17 to the input terminal group 15. On the other hand, when the data register 2 delivers the digital signal in the input terminal group 4 to the output terminal group 5, the data register 8 outputs, to the output terminal group 18, the digital signal indicative of the other data supplied from the fixed data generating circuit 17 to the input terminal group 16. The one data from the fixed data generating circuit 17 is one from which the D/A converter 14 can generate an external reference voltage V which is necessary to deliver to an output terminal 20 an analog signal extended in a predetermined manner from the input digital signal having an information area wider than one half of the full scale. The other data from the fixed data generating circuit 17 is one from which the D/A converter 14 can generate an external reference voltage V/2 which is necessary to deliver to the output terminal 20 an analog signal corresponding to the digital input signal having an information area narrower than one half of the full scale.
By the way, there is disclosed in Japanese Patent laid-open Gazette No. 58-115925 a D/A converter using a switched capacitor.